This invention pertains to a semiconductor integrated circuit (SIC) with scan chains and to a method of generating a testing sequence for fault detection in an SIC.
Conventionally, scan chains formed of scan flip-flops have been used for in-SIC fault detection.
A conventional way of testing a semiconductor integrated circuit for the presence or absence of a fault by means of a scan chain is explained below.
Referring now to FIG. 25, there is shown an SIC 50 with scan chains. 51, 52, and 53 are scan flip-flops. 54 is an AND gate.
Each flip-fop 51, 52, 53 operates as a usual flip-flop when PIN NT is in the state of logical 0 and takes in the state of PIN D as an internal-state on the rising edge of the clock applied to PIN CLK, which is called NORMAL MODE. When PIN NT is in the state of logical 1, on the other hand, each flip-flop 51, 52, 58 takes in the state of PIN DT as an internal state on the rising edge of the clock applied to PIN CLK, which is called SCAN MODE.
PIN DT of the flip-flop 51 is connected to SCAN-IN PIN SI. PIN DT of the flip-flop 52 is connected to PIN Q of the flip-flip 51. PIN DT of the flip-flop 53 is connected to PIN Q of the flip-flop 52. Additionally, PIN Q of the flip-flip 53 is connected to SCAN-OUT PIN SO. That is, in the SCAN MODE, the flip-flops 51, 52, 53 together constitute a shift register with an input terminal (i.e., PIN SI) and an output terminal (i.e., PIN SO). This is called a scan chain.
The shift operation of such a scan chain enables the state of the scan flip-flop to be set as well as to be observed with ease. This facilitates in-SIC fault detection.
A testing sequence for use in in-SIC fault detection is described taking a circuit of FIG. 25 for example.
In order to check SIGNAL LINE A for the presence or absence of a stuck-at-1 fault, it is sufficient to observe the state of SIGNAL LINE Y at the time when SIGNAL LINE A is set at a logical-0 state and SIGNAL LINE B is set at a logical-1 state. If SIGNAL LINE Y is found having a logical-0 state, this indicates that SIGNAL LINE A is good. On the other hand, if SIGNAL LINE Y is found having-a logical-1 state, this indicates that SIGNAL LINE A is in the state of stuck-at-1 fault.
The states of SIGNAL LINES A and B can be set easily making use of scan chains. More specifically, PIN NT is made to have a logical-1 state, whereupon the flip-flops 51, 52, 53 enter the SCAN MODE. A logical-1 and then a logical 0 are taken in at PIN SI to perform shift operations. Thereafter, the flip-flop 52 takes in a logical 1 while the flip-flop 51 takes in a logical 0.
The state of SIGNAL LINE Y can be observed with ease making use of scan chains. More specifically, PIN NT is made to have a logical-0 state, whereupon the flip-flops 51, 52, 53 enter the NORMAL MODE. Normal operations are performed for one clock so as to have the flip-flop 53 take in the state of SIGNAL LINE Y from PIN D. Thereafter, the state of PIN NT is brought to a logical-1 state, whereupon the flip-flops 51, 52, 53 enter the SCAN MODE and shift operations cause PIN SO to provide the state of SIGNAL LINE Y.
FIG. 26 is a table showing data of individual input/output pins of the SIC 50 at the time when performing the above-described operations. "0s" are logical-0 inputs, "1s" are logical-1 inputs, "Ls" indicate that an expected value as output is logical 0, and "Xs" mean "Don't Care".
Shift-in operations are performed in the SCAN MODE (NT=1) at times t0-t5. At t0 and t1, values to be set to the flip-flop 53 are taken in at PIN SI. There is no need for the flip-flip 53 to be set at a specific logical state and the input is "Don't Care". At t2 and t3, a value is taken in at PIN S1 for setting to the flip-flop 52. The flip-flop 52 is to be set at a logical-1 state and the input is a logical 1. At t4 and t5, a value is taken in at PIN S1 for setting to the flip-flop 51. The flip-flop 51 is to be set at a logical 0 state and the input is a logical 0. The shift-in operations are completed here.
At t6 and t7, the flip-flop 53 takes in the state of SIGNAL LINE Y in the NORMAL MODE (NT=0).
Shift-out operations are performed in the SCAN MODE (NT=1) at t8 to t13. At t8 and t9, an expected value held in the flip-flop 53 is provided at PIN SO. If the expected value is logical 0, then the signal line is judged to be good. On the other hand, if the expected value is logical 1, then the signal line is judged to suffer from a fault. At t10 and t11, values held in the flip-flop 52 are provided at PIN SO. At t12 and t13, values held in the flip-flip 51 are provided at PIN SO. The shift-out operations are completed here.
Data patterns, shown in FIG. 26, are called a testing sequence. Data are shifted one position on the rising edge of the clock and two rows of a testing sequence correspond to one shift pattern. Various methods of generating testing sequences for use in in-SIC fault detection have been proposed.
The prior art techniques, however, have disadvantages as follows.
Conventionally, generation of testing sequences is performed on an entire SIC. In other words, testing sequence generation for performing a series of operations on an entire SIC (e.g., inputting data at an input pin, shifting input data into a scan chain, shifting data for comparison with an expected value out of a scan chain, and providing data at an output pin) is performed. This may not produce serious problems as long as the scale of SIC is small. However, in recent years, as integration technology advances the scale of SIC increases. As a result, testing sequence generation becomes a time consuming process. Recently, testing sequences are generated automatically with the aid of computers; however, because of remarkable improvement in the degree of integration, the prior art testing sequence generation techniques require not only a tremendous length of time for generation of testing sequences but also a tremendous amount of memory storage for compaction of the length of testing sequences.